The application by Peter Zdebel et al., entitled "Integrated Circuit Structures Having Polycrystalline Electrode Contacts and Process", Ser. No. 07/009,322, is related.
This invention relates generally to a means and method for fabricating an integrated circuit structure, and more particularly, to a means and method for fabricating an integrated transistor in a single crystal semiconductor region enclosed by an isolation wall.
There is a need in the integrated circuit art for obtaining smaller and smaller devices without sacrificing device performance. Small device size requires small device regions, precise alignment between regions and minimization of parasitic resistances and capacitances. Device size can be reduced by putting more reliance on fine line lithography, but as device shrinking continues, it becomes impractical or impossible to continue to reduce feature size and achieve the required greater and greater alignment accuracy. As lithography is pushed to the limit, yield and production throughput decrease. Thus, a need continues to exist for means and methods for manufacturing high performance semiconductor devices, especially transistors, having smaller total area and where the critical device regions have extremely small dimensions and are located with respect to each other without need for critical alignment steps.
Accordingly, it is an object of this invention to provide an improved process and structure for fabricating integrated circuit devices, particularly transistors.
It is another object of this invention to provide an improved process and structure for producing integrated circuit devices, particularly transistors, of reduced size with practicable photolithographic tolerance.
It is yet another object of this invention to provide an improved process and structure for NPN and PNP transistors wherein the device contacts are separated by the minimum lithographic spacing capability.
It is a still further object of this invention to provide an improved process and structure for producing vertical NPN or PNP transistors in a single semiconductor tub, laterally surrounded by an insulating isolation region.
As used herein, the words "block-out mask" are intended to refer to a mask or its corresponding image in various device layers, which provides one or more open regions and closed regions which need not be precisely aligned to preceding fabrication patterns or masks. A block-out mask is typically used to protect openings and/or other areas of the structure created by one or more earlier masks from etching or implantation steps which are for example, intended to proceed through the combination of the open regions of the block-out mask and other openings in earlier masks or layers.
The word "intrinsic" in connection with a base region or the like is used herein to refer to the active portion of the base of a transistor between the emitter and collector or equivalent. The word "extrinsic" in connection with a base region or the like is used herein to refer to the inactive portion of the base or the like, for example, the portion of a bipolar transistor base laterally exterior to the intrinsic base region, and which is typically used to provide contact to the intrinsic base region.